Immersion process for electroplating applications

ABSTRACT

A method for immersing a substrate into a plating solution. In one embodiment, the method includes applying a first waveform to the substrate as the substrate is being immersed into the plating solution, stopping the application of the first waveform to the substrate as soon as the substrate is fully immersed inside the plating solution, and applying a second waveform to the substrate prior to the substrate being situated into a plating position.

BACKGROUND OF THE INVENTION

1. Field of the Invention

Embodiments of the present invention generally relate to a method forimmersing a semiconductor substrate into a processing fluid.

2. Description of the Related Art

Metallization of sub-quarter micron sized features is a foundationaltechnology for present and future generations of integrated circuitmanufacturing processes. More particularly, in devices such asultra-large-scale-integration devices, i.e., devices having integratedcircuits with more than a million logic gates, the multilevelinterconnects that lie at the heart of these devices are generallyformed by filling high aspect ratio, i.e., greater than about 3:1,interconnect features with a conductive material, such as copper.Conventionally, deposition techniques such as chemical vapor deposition(CVD) and physical vapor deposition (PVD) have been used to fill theseinterconnect features. However, as the interconnect sizes decreaseand/or aspect ratios increase, void-free interconnect feature fill viaconventional metallization techniques becomes increasingly difficult.Therefore, plating techniques, i.e., electrochemical plating (ECP) andelectroless plating, have emerged as standard processes for void freefilling of sub-quarter micron sized high aspect ratio interconnectfeatures in integrated circuit manufacturing processes.

In an ECP process, for example, sub-quarter micron sized high aspectratio features formed into the surface of a substrate (or a layerdeposited thereon) may be efficiently filled with a conductive material.ECP plating processes generally involve two stages, wherein a seed layeris first formed over the surface features of the substrate (generallythrough PVD, CVD, electroless, electrolytic, or other depositionprocess), and then the surface features of the substrate are exposed toan electrolyte solution, while an electrical bias is applied between theseed layer and a copper anode positioned within the electrolytesolution. The electrolyte solution generally contains a source of metalthat is be plated onto the surface of the substrate, and therefore, theapplication of the electrical bias causes the metal source to be platedonto the biased seed layer, thus depositing a layer of the ions on thesubstrate surface that fills the features.

However, one challenge associated with ECP processes is that the platingsolutions, which are generally acidic, may chemically etch the seedlayer during the process of immersing the substrate in the platingsolution. Inasmuch as seed layers are generally relatively thinconductive layers, the chemical etching that may take place during theimmersion process may result in conductive discontinuities in the seedlayer, which may cause plating irregularities in the subsequent platingprocesses. Therefore, in order to prevent chemical etching during theimmersion process, conventional electroplating systems apply anelectrical loading bias to the substrate seed layer during the immersionprocess. The loading bias is generally configured to apply a cathodicbias to the substrate in order to prevent the chemical etching processand to cause at least some forward plating to occur. In a conventionalprocess, the loading bias is a constant voltage applied to the substrateas the substrate is immersed in the plating solution and is maintaineduntil the wafer reaches its plating position. The loading bias must behigh enough to protect the seed layer from chemical etching and is inmany cases higher for thinner seeds. In general, smaller featuresrequire thinner seeds. Therefore, as features become smaller, therequired loading bias increases. It may also be desirable to furtherincrease the loading bias beyond the level required to protect the seedlayer in order to enhance nucleation of the electrodeposit.

However, for smaller features (e.g., about 65 nm or smaller), theconventional process is subject to failure for a number of problems. Forexample, the loading bias applied during the immersion may fill smallfeatures if it is sustained until the plating position is reached.However, this can lead to the formation of undesirable pinch-off voids.A pinch-off void is typically created when the current density on thesidewalls of a feature is high enough compared to the current density atthe bottom of the feature such that the feature opening closes beforethe feature is fully filled. Further, in the early stages of theimmersion process, i.e., when the substrate first contacts the platingsolution, very high current densities have been detected across the wetarea of the substrate. These initially high current densities canintroduce extremely undesirable effects, such as surface defects, gasbubbles and non-uniform conditions across the surface of the substrate.Further, as the surface of the substrate is immersed in the tiltingmotion under the constant load bias, the conductive area of thesubstrate being immersed is changing (increasing), and therefore, theresistance of the conductive path is also changing (decreasing). As aresult of the changes in the current path during the immersion process,the current density applied across the surface of the substrate variesthrough the immersion process. Although the immersion process may onlytake a few seconds, the uniformity of the initial electrodeposit may beaffected by the varying current density applied across the surface ofthe seed layer, and therefore, the uniformity of layers subsequentlyplated over the seed layer may also be affected.

Therefore, a need exists in the art for an improved method forcontrolling the current density on the substrate during immersion.

SUMMARY OF THE INVENTION

One or more embodiments of the present invention are generally directedto a method for immersing a substrate into a plating solution. Themethod includes applying a first waveform to the substrate as thesubstrate is being immersed into the plating solution, stopping theapplication of the first waveform to the substrate as soon as thesubstrate is fully immersed inside the plating solution, and applying asecond waveform to the substrate prior to the substrate being situatedinto a plating position.

BRIEF DESCRIPTION OF THE DRAWINGS

So that the manner in which the above recited features of the presentinvention can be understood in detail, a more particular description ofthe invention, briefly summarized above, may be had by reference toembodiments, some of which are illustrated in the appended drawings. Itis to be noted, however, that the appended drawings illustrate onlytypical embodiments of this invention and are therefore not to beconsidered limiting of its scope, for the invention may admit to otherequally effective embodiments.

FIG. 1 illustrates a plating cell that may be used in connection withone or more embodiments of the invention.

FIG. 2 illustrates a sectional view of the plating cell and a headassembly during an immersion process.

FIG. 3 illustrates a time diagram of an immersion process in connectionwith one or more embodiments of the invention.

FIG. 4 illustrates a flow diagram of a method for immersing a substrateinto a plating solution in accordance with one or more embodiments ofthe invention.

FIG. 5 illustrates the total current supplied to a substrate inaccordance with an embodiment of the invention as compared to prior art.

DETAILED DESCRIPTION

FIG. 1 illustrates an exemplary plating cell 100 that may be used inconnection with one or more embodiments of the invention. The platingcell 100 generally includes an outer basin 101 and an inner basin 102positioned within outer basin 101. Inner basin 102 is generallyconfigured to contain a plating solution that is used to plate a metal,e.g., copper, onto a substrate during an electrochemical platingprocess. During the plating process, the plating solution is generallycontinuously supplied to inner basin 102, and therefore, the platingsolution continually overflows the uppermost point (generally termed a“weir”) of inner basin 102 and is collected by outer basin 101 anddrained therefrom for chemical management and recirculation. Platingcell 100 may be generally positioned at a tilt angle, i.e., the frameportion 103 of plating cell 100 may generally be elevated on one sidesuch that the components of plating cell 100 are tilted between about 3°and about 30°, or generally between about 4° and about 10° for optimalresults. The frame member 103 of plating cell 100 supports an annularbase member on an upper portion thereof. Since frame member 103 iselevated on one side, the upper generally planar surface of base member104 is generally tilted from the horizontal at an angle that correspondsto the tilt angle of frame member 103 relative to a horizontal position.Base member 104 includes an annular or disk shaped recess formed into acentral portion thereof, the annular recess being configured to receivea disk shaped anode member 105. Base member 104 further includes aplurality of fluid inlets/drains 109 extending from a lower surfacethereof. Each of the fluid inlets/drains 109 are generally configured toindividually supply or drain a fluid to or from either the anodecompartment or the cathode compartment of plating cell 100. Anode member105 generally includes a plurality of slots 107 formed therethrough,wherein the slots 107 are generally positioned in parallel orientationwith each other across the surface of the anode 105. The parallelorientation allows for dense fluids generated at the anode surface toflow downwardly across the anode surface and into one of the slots 107.

Plating cell 100 may further include a membrane support assembly 106.Membrane support assembly 106 is generally secured at an outer peripherythereof to base member 104, and includes an interior region configuredto allow fluids to pass therethrough. A membrane 108, which is generallyan ionic membrane configured to selectively allow transmission of ionstherethrough, is stretched across a lower surface of the support 206 andoperates to fluidly separate a catholyte chamber and anolyte chamberportions of the plating cell. The membrane support assembly 106 mayinclude an o-ring type seal positioned near a perimeter of the membrane,wherein the seal is configured to prevent fluids from traveling from oneside of the membrane 108 secured on the membrane support 106 to theother side of the membrane 108. A diffusion plate 110, which isgenerally a porous ceramic disk member is configured to generate asubstantially laminar flow or even flow of fluid in the direction of thesubstrate being plated, may optionally be positioned in the cell betweenmembrane 108 and the substrate being plated. A more detailed descriptionof the plating cell 100 may be found in commonly assigned U.S. patentapplication Ser. No. 10/781,040, which was filed on Feb. 18, 2004 underthe title “METHOD FOR IMMERSING A SUBSTRATE”, claiming priority to U.S.Provisional Application Ser. No. 60/448,575, which was filed on Feb. 18,2003, both of which are incorporated herein by reference in theirentireties to the extent that these applications are not inconsistentwith the present invention. Although one or more embodiments aredescribed with referenced to a tilted plating cell, such as plating cell100, other embodiments may be implemented in other types of platingcells, such as one described in commonly assigned U.S. patentapplication Ser. No. 10/135,546, which was filed on Apr. 29, 2002 underthe title “APPARATUS AND METHOD FOR REGULATING THE ELECTRICAL POWERAPPLIED TO A SUBSTRATE DURING IMMERSION,” which is incorporated hereinby reference.

FIG. 2 illustrates an exemplary head assembly 200 used in connectionwith the plating cell 100. The head assembly 200 may include a contactring 202 and a thrust plate assembly 204. A more detailed description ofthe contact ring 202 and thrust plate assembly 204 may be found incommonly assigned U.S. patent application Ser. No. 10/278,527, which wasfiled on Oct. 22, 2002 under the title “PLATING UNIFORMITY CONTROL BYCONTACT RING SHAPING”, and commonly assigned U.S. Pat. No. 6,251,236entitled “CATHODE CONTACT RING FOR ELECTROCHEMICAL DEPOSITION,” both ofwhich are hereby incorporated by reference in their entirety to theextent not inconsistent with the present invention.

The substrate may be secured to the contact ring 202, and the lowerportion of the head assembly 200, i.e., the combination of the contactring 202 and the thrust plate assembly 204, may be positioned at a tiltangle. The lower portion of head assembly 200 and the plating surface ofthe substrate positioned on the contact ring 202 may be tilted to thetilt angle as a result of the movement of head assembly 200. The tiltangle is defined as the angle between horizontal and the platingsurface/production surface of the substrate secured to the contact ring202. The tilt angle is generally between about 3° and about 30°, andmore particularly, between about 3° and about 10°. Further, pivot point208 may be positioned such that when the head assembly is tilted, acentral vertical axis of the substrate remains in substantially the samelocation as when the substrate was positioned horizontally, i.e., thepivot point 208 may be positioned proximate contact ring 202.

Once the head assembly 200 is tilted, it may be actuated in theZ-direction to begin the immersion process. As the head assembly 200 ismoved toward plating cell 100, the lower side of contact ring 202contacts the plating solution as the head assembly 200 is actuatedtoward plating cell 100. The process of actuating head assembly 200toward plating cell 100 may further include imparting rotationalmovement to contact ring 202. Thus, during the initial stages of theimmersion process, contact ring 202 may be actuated in a vertical orZ-direction, while also being rotated about a central axis thatintersects the radial center of the substrate, which is also generallyorthogonal to the substrate surface.

As the substrate becomes immersed in the plating solution containedwithin plating cell 100, the Z-motion of head assembly 200 may be slowedand/or terminated and the tilt position of contact ring 202 may bereturned to horizontal. This process generates a unique movement thatincludes both vertical actuation and tilt angle actuation, which hasbeen shown to reduce bubble formation and adherence to the substratesurface during the immersion process. Further, the vertical and pivotalactuation of the substrate during immersion process may also includerotational movement of contact ring 202, which has been shown to furtherminimize bubble formation and adherence to the substrate surface duringthe immersion process.

Once the substrate is completely immersed into the plating solutioncontained within the plating cell 100, the head assembly 200 may furtherbe actuated in a vertical direction (downward) and be pivoted aboutpivot point 208, to further immerse the substrate into the platingsolution. Once the substrate is positioned deeper within the platingsolution, the head assembly 200 may again be pivoted about pivot point208, so the substrate surface may be positioned in parallel relationshipto the upper surface of the anode 105. These various processes may alsoinclude rotating the substrate, which operates to dislodge any bubblesformed during the immersion process from the substrate surface.

FIG. 3 illustrates a time diagram 300 of an immersion process inconnection with one or more embodiments of the invention. Stage 310refers to a time period during which the substrate is immersed into theplating solution. The time period covered by stage 310 spans from whenthe substrate first contacts the plating solution to when the substrateis fully immersed. In one embodiment, stage 310 lasts from about 0.10seconds to about 1.0 second. Stage 320 refers to a time period from themoment the substrate is fully immersed to the moment the substrate issituated in a plating position. In one embodiment, stage 320 lasts fromabout 1 second to about 5 seconds. Stage 330 refers to a time periodduring which the substrate is in a plating position. The platingposition is defined as the position during which a conventional platingwaveform is applied to completely fill the largest features on thesubstrate and overplate the substrate to a final total thickness.

FIG. 4 illustrates a flow diagram of a method 400 for immersing asubstrate into a plating solution in accordance with one or moreembodiments of the invention. At step 410, a first waveform is appliedto the substrate as the substrate is immersed into the plating solution.A waveform is a sequence of voltages or currents designed to control thecurrent density on the substrate surface. The waveform may comprise aconstant voltage or current, a series of voltage or current steps, agradually or periodically varying voltage or current, a pulsed voltageor current, or any combination of the above. When the waveform involvesapplying a voltage, the voltage may be applied to the entire cell or tothe substrate relative to a reference electrode 250 disposed inside theplating solution, as shown in FIG. 2. The waveforms discussed herein maybe implemented in several ways. These ways include varying the voltageor current under recipe control, in response to a substrate positionsensor, or in response to a direct measure of voltage or current passingthrough the cell. Recipe control is defined as applying a waveform inwhich the voltage or current are varied in time in a predeterminedmanner based on the expected trajectory of the substrate. As such,recipe control is distinct from schemes where the applied voltage orcurrent vary in response to a sensor that actively detects the position,voltage, or current on the substrate in real time. Recipe control may benecessary for certain advanced processes where the time period overwhich the voltage or current must be varied is so short such that thereis insufficient time to send the sensor signal, communicate it to thecontrol system such as a computer, and analyze it before applying thenext voltage or current. A typical implementation of recipe controlinvolves performing a number of experiments or calculations to identifythe desired duration for each voltage or current to be applied. Onceknown, these voltages and currents constitute a predetermined waveformthat can be applied thereafter every time a substrate is processed.

In view of FIG. 3, step 410 occurs during stage 310. As such, the timeperiod during which the first waveform is applied may last from themoment the substrate first contacts the plating solution to the momentthe substrate is fully immersed. That time period may last from about0.10 seconds to about 1.0 second. In one embodiment, the first waveformincludes a constant voltage. Surprisingly, the first waveform mayinclude a voltage such that the resulting current density on thesubstrate exceeds the threshold for pinch-off voids. This threshold is apredetermined current density that would lead to the formation ofpinch-off voids if maintained throughout stages 310 and 320. Thepredetermined threshold required to create a pinch-off void is primarilya function of feature size; however, it may also be a function ofplating solution chemistry and seed layer profile and thickness.

In yet another embodiment, the first waveform comprises a voltage thatis ramped, i.e., increases over time. In still another embodiment, thefirst waveform comprises a sequence of voltages that increases overtime. In still yet another embodiment, the first waveform comprises avoltage that is stepped or multistepped, i.e., includes two or moreconstant voltages, wherein each successive voltage is different from theprevious voltage. In such embodiments, application of the first waveformis configured to ensure that the feature filling process occurs at allpoints on the substrate within a suitable current density window and tofacilitate uniform deposition of metal ions across the substrate.Although the first waveform has been described as being voltagecontrolled, other embodiments of the invention contemplate the firstwaveform as being current controlled.

In yet another embodiment, applying the first waveform includes applyinga first voltage to the substrate as the substrate first contacts theplating solution, stopping the application of the first constant voltageto the substrate after a predetermined period of time (or after apredetermined amount of current supplied to the substrate is reached),and supplying a first current to the substrate from the moment thepredetermined period of time ends (or from the moment the predeterminedamount of current is reached) to the moment the substrate is completelyimmersed. When the substrate first contacts the plating solution, thereis a short period of time during which the plating solution climbs upthe substrate surface due to capillary forces, thereby creating awicking effect. This wicking effect may cause a high current density onthe wet area of the substrate since the wet area is small and the cellresistance is low. Accordingly, the first constant voltage may beconfigured to take into account this wicking effect. As the substrate isbeing immersed into the plating solution, the fluid dynamics of the wetarea of the substrate changes. As such, the first current is configuredto take into account the fluid dynamics changes in vertical velocity,swing motion and rotation of the substrate and capillary forces of theplating solution. Further, the first constant voltage and the firstcurrent may each be a function of seed layer thickness, feature size,plating solution concentration, substrate size and plating cellgeometry/design.

Referring now to step 420, once the substrate is fully immersed,application of the first waveform is stopped and a second waveform isapplied to the substrate from the time the substrate is fully immersedto the time the substrate is situated into a plating position. In oneembodiment, step 420 occurs during stage 320. As such, the time periodduring which the second waveform is applied lasts from the moment thesubstrate is fully immersed to the moment the substrate is situated in aplating position. The second waveform may be applied for about 1 secondto about 5 seconds. In this manner, the first and second waveforms areapplied to the substrate prior to the substrate being situated in theplating position. However, the second waveform may also continue to beapplied to the substrate for a predetermined period of time after thesubstrate is situated in the plating position (stage 330).

In one embodiment, the second waveform includes a constant current. Inanother embodiment, the second waveform includes a current less than apredetermined threshold configured to perform a bottom-up fill. Thepredetermined threshold required to initiate a bottom-up fill istypically a function of feature size, plating solution chemistry andseed layer thickness. A bottom-up fill refers to a higher rate ofdeposition at the bottom of a feature than at the sidewalls. In such anembodiment, application of the second waveform may be configured to growand thicken a conformal metal layer on the seed layer prior to fillingthe features or prior to a bottom-up fill.

In another embodiment, the second waveform includes a current thatstarts from below about a predetermined threshold configured to performa bottom-up fill and increases as the thickness of a layer of depositfrom the plating solution to the substrate increases. In such anembodiment, in addition to growing and thickening a conformal metallayer on the seed layer prior to filling the features or prior to abottom-up fill, application of the second waveform may be configured toensure that the feature filling process occurs at all points on thesubstrate within a suitable current density window and to facilitateuniform deposition of metal ions across the substrate.

In yet another embodiment, step 420 may include application of a pulsedvoltage or current prior to the application of the various embodimentsof second waveform described above. The pulsed voltage or current may begreater than a predetermined threshold configured to create a pinch-offvoid inside a feature. In such an embodiment, the pulsed voltage orcurrent may be configured to enhance or attract metal ions containedinside the plating solution to portions of the substrate where the seedlayer coverage is thin, patchy or completely absent.

Once the substrate is situated in the plating position, a platingwaveform is applied to the substrate (step 430). The plating waveform isdefined as a waveform designed to complete the filling of the largestfeatures on the substrate and overplate the substrate to the desiredfinal thickness of the deposit. For example, a plating waveform mayconsist of a sequence of one or more constant current steps. In oneembodiment, application of the second waveform is stopped before thesubstrate is situated in the plating position and the plating waveformis applied to the substrate while the substrate is still being situatedinto the plating position. In another embodiment, the second waveformcontinues to be applied to the substrate for a predetermined period oftime while the substrate is in the plating position before the platingwaveform is applied.

A specific example is described below to further illustrate theinvention. During stage 310, a first waveform having a constant cellvoltage of 2 V, which corresponds to a current density of 5 mA/cm² on afully immersed substrate, is applied for about 0.7 sec. During stage320, a second waveform having a constant current equivalent to 3 mA/cm²is applied for about 1 to 4 seconds. This is followed by a typicalplating waveform which is a sequence of three constant-current stepsbeginning at the end of stage 320. An example of the plating waveformincludes depositing 500 Å at a current density of 5 mA/cm², followed bydepositing 1000 Å at a current density of 10 mA/cm², and followed bydepositing 8500 Å at a current density of 40 mA/cm². The above exampleapplies to the case of a 300 mm wafer with a 500 Å seed layer, trenchfeatures that are 55 nm wide and 150 nm deep, and via features that are80 nm in diameter and 360 nm deep. The plating bath used contained 40g/L copper, 10 g/L acid, 50 ppm chloride, and optimized concentrationsof plating additives such as the Enthone Viaform accelerator,suppressor, and leveler. For comparison, an example of the prior art mayinclude applying a cell voltage of 2 V for the duration of stages 310and 320, then applying a typical plating waveform from the end of stage320. An example of the invention in view of a prior art example isillustrated in FIG. 5, which shows the total current supplied to thesubstrate as a result of the applied waveforms. While the prior artexample is suitable for larger feature sizes, it often leads tosignificant pinch-off voids for the feature sizes mentioned above.

While the foregoing is directed to embodiments of the present invention,other and further embodiments of the invention may be devised withoutdeparting from the basic scope thereof, and the scope thereof isdetermined by the claims that follow.

1. A method for immersing a substrate into a plating solution,comprising: applying a first waveform to the substrate as the substrateis being immersed into the plating solution; stopping the application ofthe first waveform to the substrate as soon as the substrate is fullyimmersed inside the plating solution; and applying a second waveform tothe substrate prior to the substrate being situated into a platingposition.
 2. The method of claim 1, further comprising: stopping theapplication of the second waveform once the substrate is situated in theplating position; and applying a plating waveform to the substrate. 3.The method of claim 1, wherein the first waveform comprises a constantvoltage.
 4. The method of claim 1, wherein the first waveform comprisesa voltage greater than a predetermined threshold for creating apinch-off void inside a feature.
 5. The method of claim 1, wherein thefirst waveform comprises a voltage that increases over time.
 6. Themethod of claim 1, wherein the first waveform comprises a sequence ofvoltages that increases over time.
 7. The method of claim 1, wherein thefirst waveform comprises a first constant voltage and a second constantvoltage higher than the first constant voltage.
 8. The method of claim1, wherein applying the first waveform comprises: applying a firstconstant voltage to the substrate as the substrate first contacts theplating solution; stopping the application of the first constant voltageto the substrate after a predetermined period of time and prior to thesubstrate being fully immersed in the plating solution; and supplying acurrent to the substrate from the moment the predetermined period oftime ends to the moment the substrate is completely immersed.
 9. Themethod of claim 8, wherein the predetermined period of time is fromabout 0.10 seconds to about 1.0 second.
 10. The method of claim 1,wherein applying the first waveform comprises: applying a first constantvoltage to the substrate as the substrate first contacts the platingsolution; stopping the application of the first constant voltage to thesubstrate after a predetermined current supplied to the substrate isreached; and supplying a current to the substrate from the moment thepredetermined current supplied to the substrate is reached to the momentthe substrate is completely immersed.
 11. The method of claim 1, whereinthe first waveform is applied to the substrate from about 0.10 secondsto about 1.0 second.
 12. The method of claim 1, wherein the secondwaveform comprises a constant current.
 13. The method of claim 1,wherein the second waveform comprises a current less than apredetermined threshold for performing a bottom-up fill.
 14. The methodof claim 4, wherein the second waveform comprises a current less than apredetermined threshold for performing a bottom-up fill.
 15. The methodof claim 1, further comprising stopping the application of the secondwaveform before the substrate is situated in the plating position; andapplying a plating waveform to the substrate while the substrate isstill being situated into the plating position.
 16. The method of claim4, further comprising stopping the application of the second waveformbefore the substrate is situated in the plating position; and applying aplating waveform to the substrate while the substrate is still beingsituated into the plating position.
 17. The method of claim 13, furthercomprising stopping the application of the second waveform before thesubstrate is situated in the plating position; and applying a platingwaveform to the substrate while the substrate is still being situatedinto the plating position.
 18. The method of claim 1, wherein the secondwaveform comprises a current that starts from below a predeterminedthreshold for performing a bottom-up fill and increases as the thicknessof a layer of deposit from the plating solution to the substrateincreases.
 19. The method of claim 4, wherein the second waveformcomprises a current that starts from below a predetermined threshold forperforming a bottom-up fill and increases as the thickness of a layer ofdeposit from the plating solution to the substrate increases.
 20. Themethod of claim 18, further comprising stopping the application of thesecond waveform before the substrate is situated in the platingposition; and applying a plating waveform to the substrate while thesubstrate is still being situated into the plating position.
 21. Themethod of claim 1, wherein the second waveform comprises a pulsedcurrent or a pulsed voltage.
 22. The method of claim 4, wherein thesecond waveform comprises a pulsed current or a pulsed voltage.
 23. Themethod of claim 1, wherein the first waveform and the second waveformare applied under recipe control.
 24. The method of claim 1, furthercomprising immersing the substrate at an angle.